This invention relates generally to semiconductor or other electrical device fabrication, and more particularly, to fabrication of structures with through substrate vias, including semiconductor structures with through substrate vias, and other electrical devices, such as microelectromechanical systems (MEMS), manufactured on a substrate with through substrate vias.
As semiconductor scaling faces difficulty at device dimensions approaching atomic scale, three-dimensional device integration offers a method for increasing density of semiconductor devices within a device. In three-dimensional integration, a plurality of semiconductor die or chips may be vertically stacked with electrical contacts disposed on both the active surfaces and the back surfaces of the chips so as to increase electrical interconnections between the stacked chips.
Through substrate vias (TSVs) (or through silicon vias) facilitate, at least in part, this electrical interconnection. Typically, a through substrate via extends from the active surface or side (for example, from a line-level metal wiring structure on the front surface, which is typically a first metal wiring level in a metal interconnect structure) to the back surface or side of the semiconductor die or chip. These through substrate vias provide electrical connection paths through the substrate of the semiconductor chip, for example, to facilitate electrically interconnecting a plurality of stacked semiconductor chips.